1. Field of the Invention
The present invention relates to technique of generating a wiring pattern employed in the process of manufacturing a chip-first system in package or a wafer level package, and technique of exposing the wiring pattern.
2. Description of the Background Art
In the process of manufacturing a chip-first SIP (system in package) or a WLP (wafer level package), a redistribution layer is used in connecting ICs (integrated circuits) or connecting a pad of an IC and a bump. At this time, a problem is generated about how to correct a configuration error of an IC bonded on a substrate to become a support base.
Japanese Patent Application Laid-Open No. 2003-197850 and US Publication No. 2010/0213599 disclose technique of using a stepper for exposure. According to this technique, the position and the angle of exposure through a mask are controlled finely within a range of the exposure, thereby avoiding the aforementioned problem. However, yield is reduced if there is a serious configuration error of an IC. As an example, if a distance between ICs to be connected does not fall below the length of a wiring pattern capable of being exposed through the mask, connection failure may be generated in a redistribution layer. Further, if circuit areas regarding a plurality of ICs on a substrate are to be exposed simultaneously and if configuration errors of the ICs are not the same, connection failure cannot be controlled easily.
Meanwhile, according to known technique regarding exposure, a beam for exposure is scanned without using a mask. This technique makes it possible to correct a configuration error of an IC more easily than the technique of using a mask. To be specific, if a configuration error is generated, a wiring pattern is redesigned from the beginning, and wiring data indicating the corrected wiring pattern is generated in a mask CAD format such as a GDS format. A RIP (raster image processor) performs raster image processing for an imaging system on the resultant wiring data to generate imaging data in a raster format, thereby realizing redistribution by the imaging system. However, generation of wiring data by the redesign of a pattern takes up a great deal of time. The raster image processing also takes up a great deal of time. In response, technique intended to reduce time required for generating wiring data responsive to a configuration error has been suggested in exposure by beam scanning not using a mask.
As an example, the imaging system disclosed in Japanese Patent Application Laid-Open No. 1-205022 (1989) detects the position displacement of an alignment mark assigned to each circuit area on a substrate as the position displacement of an electrode in the corresponding circuit area. Then, the system corrects a wiring pattern, to connect circuit areas when the circuit areas are placed as designed and no position displacement is generated, by horizontally shifting a part of the wiring pattern within the circuit areas in response to position displacement. At the same time, the system performs imaging by beam scanning based on the corrected wiring pattern. However, if not only position displacement but also angle displacement is generated in each circuit area, displacement of an alignment mark and displacement of an electrode being an end point of the wiring pattern do not agree with each other. Hence, the system of Japanese Patent Application Laid-Open No. 1-205022 cannot avoid generation of connection failure in a redistribution layer.
The imaging system disclosed in Japanese Patent Application Laid-Open No. 2012-42587 compares an image formed by photographing a substrate on which each IC with a plurality of electrodes is placed and an existing wiring pattern for this substrate in the absence of a configuration error of each IC, thereby specifying a combination of electrodes in a pair being opposite end points of a line connecting ICs and the respective positions of the electrodes. Then, the system obtains linear vector data used in connecting in the shortest way the specified electrodes in a pair for each electrode pair, sets the vector data thereby obtained as a wiring pattern responsive to a configuration error of an IC, and images the wiring pattern. This allows control of connection failure to occur in a distribution layer if a configuration error of an IC includes not only position displacement but also angle change.
However, the imaging system disclosed in Japanese Patent Application Laid-Open No. 2012-42587 connects an electrode of an IC and an electrode of an IC being a destination of the connection directly through a straight line in response to configuration errors of the ICs. Hence, if electrodes of each IC are placed in a complex manner such as a BGA (ball-grid array), for example, resultant wiring patterns after correction cross each other in fan-out lines leading from the BGA, for example. This results in a problem of omission of wiring (imperfect wiring) where no wiring pattern is generated.